Integrated circuit design and implementation is becoming more and more complex as the functionality and size of the circuits increase. A variety of users and manufacturers of devices utilizing integrated circuits desire an ever increasing array of functionality and performance in lower cost devices. To provide this desired array of products, producers of integrated circuit must become more efficient in the design and optimization of the circuits to ensure competitive positioning of their products.
One of the greatest hurdles in the design of an integrated circuit is the complexity encountered by the sheer numbers of components included on an integrated circuit, such as routing of the integrated circuit, timing between components of the integrated circuit, and other such “layout” considerations. To address this complexity, manufacturers of integrated circuits have to devote ever greater resources to these considerations. For example, timing closure of an integrated circuit was formerly addressed through sheer brute force, rather than through an ordered design process. Therefore, as the complexity continues to increase, the previous methods utilized to design integrated circuits will become even more insufficient for the task at hand. Such an inability to deal with complexity may lead toward a stagnation of products and a competitive disadvantage against other manufacturers that have addressed this complexity in an ordered and efficient manner.
Therefore, it would be desirable to provide a timing abstraction and partitioning strategy for integrated circuit design.